`timescale 10ns/1ns
module adder_test;
reg  ina,inb,cin;
wire sum,cout;
adder u1(ina,inb,cin,sum,cout);
initial  
  begin
    ina=0;inb=0;cin=0;
    #50 ina=1;inb=1;cin=0;
    #50 ina=1;inb=0;cin=1;
    #50 ina=0;inb=1;cin=0;
    #200 $stop;
 end
 initial 
 $monitor($time, , ,"ina=%b inb=%b  sum=%b",ina,inb,sum); 
 endmodule
